1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device. More specifically, the present invention relates to a synchronous semiconductor memory device including a buffer circuit for temporarily stopping data output from a plurality of output terminals in response to an external control signal.
2. Description of the Background Art
In a synchronous semiconductor memory device, data is input/output in synchronization with a clock signal input to the synchronous semiconductor memory device. Therefore, in such a synchronous semiconductor memory device, a clock signal generated from an external clock generating circuit for determining input or output timing is distributed to a plurality of data input/output buffers.
FIG. 8 shows a conventional circuit for distributing a clock to output buffers. Referring to FIG. 8, an internal timing clock generating circuit 1 generates, from an external clock signal ext.CLK, an internal clock signal int.CLK and distributes the generated clock signal to all output buffers 10 to 25. Data int.D&lt;0&gt; to int.D&lt;15&gt; are applied to respective output buffers 10 to 25.
In FIG. 8, an internal clock signal as a trigger for outputting data DQ&lt;0&gt; is referred to as clk&lt;0&gt;, and an internal clock signal as a trigger for outputting DQ&lt;7&gt; is referred to as clk&lt;7&gt;. Output buffers 10 to 17 output data DQ&lt;0&gt; to DQ&lt;7&gt; in synchronization with internal clock signals clk&lt;0&gt; to clk&lt;7&gt;, respectively. Similarly, output buffers 18 to 25 output data DQ&lt;8&gt; to DQ&lt;15&gt; in synchronization with internal clock signal int.CLK.
FIGS. 9A to 9D are timing charts of output data DQ&lt;0&gt;, DQ&lt;7&gt; and internal clock signals clk&lt;0&gt; and clk&lt;7&gt; shown in FIG. 8. As shown in FIGS. 9A to 9D, the time necessary for the internal clock signal int.CLK to propagate to respective output buffers differ dependent on the distance between internal timing clock generating circuit 1 and each of the output buffers 10 to 25, and therefore there is generated a skew from pin to pin in the output timing of data DQ from one same chip. If the frequency is made higher, the pin to pin skew comes to occupy larger ratio in one period, reducing timing margin for input at a controller receiving the data output from the memory. Therefore, the pin to pin skew may cause system failure.
A binary tree structure for branching the internal clock int.CLK such as shown in FIG. 10 has been proposed as means for eliminating the pin to pin skew. Referring to FIG. 10, an output from internal timing clock generating circuit 1 is divided into two by a driver circuit drv0, further divided into two by each of driver circuits drv2 and 3, and further divided into two by each of driver circuits drv6 to drv9 and applied to output buffers 10 to 17. Similarly, internal clock signal int.CLK is divided into two by driver circuit drv1, further divided into two by each of driver circuits drv4 and 5, and further divided into two by each of driver circuits drv10 to drv13 and applied to output buffers 18 to 25.
FIGS. 11A to 11E are timing charts of data output in the binary clock distributing circuit shown in FIG. 10. As can be seen from the timing charts of FIGS. 11A to 11C, internal clock signals clk&lt;0&gt; and clk&lt;7&gt; have the same propagation delay, and therefore there is not a pin to pin skew in output data DQ&lt;0&gt; and DQ&lt;7&gt;.
However, in the binary tree structure, driver circuits drv0 to drv13 are necessary at tree branching points, and therefore power consumption of the tree as a whole is considerably large. Further, in a synchronous semiconductor memory device having data input/output pins of 16 bits or more, a function referred to as byte control is provided, for masking lower or upper 8 bits of data at the time of reading or writing.
FIG. 12 is a block diagram showing a structure of a data output portion having binary tree structure with the byte control function provided additionally. Referring to FIG. 12, an input for byte control is provided commonly to output buffers 30 to 37 and 38 to 45, and by activating a DQML or DQMU signal, output is set to a high impedance state and stopped.
FIGS. 13A to 13H are timing charts of data output at the time of byte control of the output buffers shown in FIG. 12. As shown in FIG. 13C, when the signal DQML is activated, that is, set to the "H" (high) level, outputs of DQ&lt;0&gt; to DQ&lt;7&gt; are set to the high impedance state as shown in FIG. 13G in synchronization with a rise of internal clocks clk&lt;0:7&gt; shown in FIG. 13E, and when the signal DQMU shown in FIG. 13D is set to the "H" level, data outputs DQ&lt;8&gt; to DQ&lt;15&gt; are set to the high impedance state as shown in FIG. 13H in synchronization with internal clocks clk&lt;8:15&gt; shown in FIG. 13F.
FIG. 14 is a specific circuit diagram of the output buffer shown in FIG. 12. Referring to FIG. 14, data int.D&lt;n&gt; is applied to the drain and internal clock signal int.clk&lt;n&gt; is applied to the gate of n channel MOS transistor 301 of output buffer 30. When transistor 301 turns on in response to the internal clock signal, data is latched in a latch circuit consisting of inverters 302 and 303 connected to the emitter of the transistor. An output from the latch circuit is applied to one input end of an AND gate 306, and applied, inverted by inverter 304, to one input end of an NAND gate 305.
To the other input end of NAND gate 305 and to the other input end of AND gate 306, the signal DQML or DQMU is applied. An output of NAND gate 305 is applied to the gate of a p channel MOS transistor 307, an output of AND gate 306 is applied to the gate of an n channel MOS transistor 308, and output signal DQ&lt;n&gt; is output from the drains of transistors 307 and 308. A power supply is connected to the source of transistor 307, while the source of transistor 308 is grounded.
In the output circuit having such a binary clock tree structure shown in FIG. 12, when byte control is performed by setting the signal DQML to "H" level to stop output of lower 8 bits, operation of output buffers 30 to 37 of lower 8 bits is stopped. However, 7 driver circuits drv0, drv2, drv3, drv6, drv7, drv8 and drv9 supplying the internal clock signal to the output buffers 30 to 37 operate continuously, consuming power.
Further, even when the binary tree structure is employed, pin to pin skew cannot always be eliminated because of process variation of the chip, or because of the difficulty in realizing perfectly symmetrical layout.